The semiconductor industry has experienced continued rapid growth due to continuous improvements in manufacturing technologies and in integration density of various electrical devices (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, the improvement in integration density has come from repeated reduction in minimum feature sizes, which allow more devices to be integrated into a given area. Technologies, such as three-dimensional (3D) integrated circuits (ICs) and through silicon vias (TSVs), are therefore created to resolve the limitations of number and lengths of interconnections between devices as the number of devices increases. Such demands have resulted in the requirement for thinner semiconductor chips.
In order to meet the requirement of thinner semiconductor chips, the semiconductor industry has incorporated wafer backside thinning (or grinding) to obtain the thinner chips or dies required. This is accomplished by removing material from the backside of the wafers after the necessary circuit patterns and/or TSVs have been fabricated on the front side of the wafers. It is within this context the following disclosure arises.